Cache Coherence Protocol (MSI)

Cache-line state transitions in the basic MSI protocol.

Template previewMermaid

Rendering…

Make it your own.

stateDiagram-v2
[*] --> Invalid
Invalid --> Shared: read miss (BusRd)
Invalid --> Modified: write miss (BusRdX)
Shared --> Modified: write (BusRdX → invalidate)
Shared --> Invalid: snoop BusRdX
Modified --> Shared: snoop BusRd (write-back)
Modified --> Invalid: snoop BusRdX (write-back)