WaveDrom
Digital timing diagrams, register maps, bit fields and bus protocols. Standard for hardware and EE research.
Templates
38
Source language
json
Workstation
Studio
Engine id
wavedrom
In the same space
Most users come to WaveDrom from Vivado timing or TimeGen. flowss runs this engine in the browser — no install, shareable via URL, exportable to PNG / SVG / PDF / source.
Syntax at a glance
{"signal":[{"name":"clk","wave":"p..."},{"name":"data","wave":"x.34.5x"}]}Paste this in the Studio code pane to see WaveDrom render live. The full grammar is at the upstream-docs link above.
Sample templates
All 38 →custom
Bus Timing
Clock, address bus, data bus with annotations.
custom
Register Bit-field
Register layout with named bit-fields.
custom
FSM-controlled Signals
Control signals driven by a finite state machine.
custom
WaveDrom — SPI bus
SPI master/slave transaction — clock, MOSI, MISO, chip-select.
custom
WaveDrom — I²C bus
I²C start, address byte, ACK, data byte, stop condition.
custom
WaveDrom — AXI Read Burst
AXI4 read burst timing — ARVALID/ARREADY handshake then 4 beats.
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