35 templates
WaveDrom templates
Digital timing diagrams, register maps, bit fields and bus protocols. Standard for hardware and EE research.
Bus Timing
Clock, address bus, data bus with annotations.
Custom / SVGRegister Bit-field
Register layout with named bit-fields.
Custom / SVGFSM-controlled Signals
Control signals driven by a finite state machine.
Custom / SVGWaveDrom — SPI bus
SPI master/slave transaction — clock, MOSI, MISO, chip-select.
Custom / SVGWaveDrom — I²C bus
I²C start, address byte, ACK, data byte, stop condition.
Custom / SVGWaveDrom — AXI Read Burst
AXI4 read burst timing — ARVALID/ARREADY handshake then 4 beats.
Custom / SVGUART Frame
8-N-1 UART frame — start bit, 8 data bits LSB first, stop bit.
Custom / SVGDDR Read Burst
Double-data-rate read — data valid on both clock edges.
Custom / SVGJTAG TAP Controller Bits
TMS sequence to navigate Test-Logic-Reset → Shift-DR.
Custom / SVGPCIe TLP Beat
PCIe TLP framing on Gen1 single-lane — STP / payload / END.
Custom / SVGPhysics — Timing: Clock Signal
A periodic digital clock with an enable line.
Scientific PlotsPhysics — Timing: D Flip-Flop
Q follows D on each rising clock edge.
Scientific PlotsPhysics — Timing: Binary Counter
A 2-bit ripple counter dividing the clock.
Scientific PlotsPhysics — Timing: SR Latch
Set and reset pulses driving the output.
Scientific PlotsPhysics — Timing: UART Serial Frame
A start bit, eight data bits and a stop bit.
Scientific PlotsPhysics — Timing: SPI Transfer
Chip-select, clock and the two data lines.
Scientific PlotsPhysics — Timing: I2C Bus
Clock and data lines during an I2C address phase.
Scientific PlotsPhysics — Timing: Shift Register
Data shifts one stage along on each clock.
Scientific PlotsPhysics — Timing: JK Flip-Flop
J, K and clock driving the toggling output.
Scientific PlotsPhysics — Timing: Johnson Counter
A twisted-ring counter's staggered outputs.
Scientific PlotsPhysics — Timing: PWM Duty Cycles
25%, 50% and 75% pulse-width modulation.
Scientific PlotsPhysics — Timing: Request-Acknowledge
A four-phase request/acknowledge data handshake.
Scientific PlotsPhysics — D-type Latch Timing
Output Q follows D while the clock is high.
Scientific PlotsPhysics — 2-bit Counter Timing
Ripple counter: each bit toggles at half the rate.
Scientific PlotsPhysics — SPI Bus Timing
Chip-select, clock and data lines of an SPI transfer.
Scientific PlotsPhysics — I2C Bus Timing
Start condition, a data byte and stop on the I2C bus.
Scientific PlotsPhysics — 4-bit Shift Register Timing
Data propagates one stage per clock pulse.
Scientific PlotsPhysics — Clock Divider Timing
Dividing a clock by two and by four.
Scientific PlotsPhysics — Finite State Machine Timing
State transitions driven by an input.
Scientific PlotsPhysics — Memory Read Cycle
Address, read strobe and data bus timing.
Scientific PlotsPhysics — Interrupt Request/Acknowledge
An interrupt handshake on a processor bus.
Scientific PlotsPhysics — 2-bit Down Counter Timing
Counts 3, 2, 1, 0 on successive clocks.
Scientific PlotsPhysics — Rising-Edge Detector
A one-clock pulse on each rising edge.
Scientific PlotsPhysics — FIFO Write/Read Timing
A value written then read from a FIFO buffer.
Scientific PlotsPhysics — Request/Acknowledge Handshake
A four-phase handshake protocol.
Scientific Plots