GPU SM Architecture

digraph sm {
  rankdir=TB;
  graph [bgcolor=transparent];
  node [shape=box, style="rounded,filled", fontname=Inter, fontsize=10];

  Sched [label="Warp schedulers ×4", fillcolor="#fef3c7"];
  Disp [label="Dispatch units"];
  Reg [label="Register file (256 KB)", fillcolor="#dbeafe"];

  Cuda [label="CUDA cores (FP32) ×128", fillcolor="#dcfce7"];
  FP64 [label="FP64 cores", fillcolor="#dcfce7"];
  Tens [label="Tensor cores", fillcolor="#dcfce7"];
  RT   [label="RT cores", fillcolor="#dcfce7"];
  Ldst [label="Load/store units"];
  Sfu  [label="Special-function units"];

  L1 [label="L1 cache + shared mem (128 KB)", fillcolor="#fce7f3"];
  Tex [label="Texture / read-only cache"];

  Sched -> Disp -> Reg;
  Reg -> Cuda; Reg -> FP64; Reg -> Tens; Reg -> RT; Reg -> Ldst; Reg -> Sfu;
  Ldst -> L1; Ldst -> Tex;
}