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Graphviz (DOT) templates

FPGA Dataflow

Pipelined dataflow on an FPGA — input → DSP blocks → output.

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digraph fpga {
  rankdir=LR;
  graph [bgcolor=transparent];
  node [shape=box, style="rounded,filled", fontname=Inter, fontsize=10];

  In [label="Input FIFO\n(AXI-Stream)", fillcolor="#dbeafe"];
  Reg1 [label="Pipeline reg", fillcolor="#ede9fe"];
  Mul [label="DSP48 ×", fillcolor="#fef3c7"];
  Reg2 [label="Pipeline reg", fillcolor="#ede9fe"];
  Add [label="DSP48 +", fillcolor="#fef3c7"];
  Reg3 [label="Pipeline reg", fillcolor="#ede9fe"];
  Out [label="Output FIFO", fillcolor="#dcfce7"];
  Coef [label="Coeff BRAM", shape=cylinder, fillcolor="#fce7f3"];

  In -> Reg1 -> Mul -> Reg2 -> Add -> Reg3 -> Out;
  Coef -> Mul;
}