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Digital logic (gates / K-map / truth table) templates

Physics — Logic: 4-bit shift register

Data ripples through four stages on each clock.

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Template previewDigital logic (gates / K-map / truth table)
4-bit shift registerDCLKF0F1F2F3Q0Q1Q2Q3Evaluated: 2 inputs, 4 outputs, 4 rows. 2 things are probably not what was meant.`Q0` and `Q2` compute the same function — they agree in all 4 rows. Either one of them is redundant, or a wire went …`Q1` and `Q3` compute the same function — they agree in all 4 rows. Either one of them is redundant, or a wire went …`CLK` is declared as an input and wired to nothing. That is deliberate in a priority encoder — the lowest line encod…Q0 = ¬DQ1 = ¬¬DQ2 = ¬¬¬D+ 1 further expressions

Make it your own.

title "4-bit shift register"
type gates
input D at (0,0)
input CLK at (0,2)
gate NOT F0 at (2,0)
gate NOT F1 at (4,0)
gate NOT F2 at (6,0)
gate NOT F3 at (8,0)
output Q0 at (3,2)
output Q1 at (5,2)
output Q2 at (7,2)
output Q3 at (9,2)
wire D F0
wire F0 F1
wire F1 F2
wire F2 F3
wire F0 Q0
wire F1 Q1
wire F2 Q2
wire F3 Q3