60 templates
Digital logic (gates / K-map / truth table) templates
Native digital-logic engine — three modes in one. `type gates` for IEC-style gate schematics (AND, OR, NOT, NAND, NOR, XOR, XNOR, BUF), `type kmap` for 2-4 variable Karnaugh maps with Gray-coded rows / columns and highlighted 1-cells, `type truthtable` for full truth tables with output-coloured cells. Covers the EE / CS undergraduate digital-logic curriculum.
Logic — half adder
Two-input half adder with XOR (sum) and AND (carry).
Chemistry & PhysicsLogic — SR latch (NAND)
Cross-coupled NAND SR latch.
Chemistry & PhysicsLogic — Karnaugh map (XOR)
2-variable K-map for the XOR function.
Chemistry & PhysicsLogic — Karnaugh map (3-input majority)
Majority function K-map (3 variables).
Chemistry & PhysicsLogic — truth table (implication)
Truth table for A implies B.
MathematicsPhysics — Logic: full adder
One-bit full adder built from two XOR, two AND and one OR gate.
Chemistry & PhysicsPhysics — Logic: 2-to-1 multiplexer
Select line steers one of two inputs to the output.
Chemistry & PhysicsPhysics — Logic: 1-bit equality (XNOR)
An XNOR gate as a single-bit comparator (A = B).
Chemistry & PhysicsPhysics — Logic: AND / OR / NOT
The three fundamental logic gates side by side.
Chemistry & PhysicsPhysics — Logic: 4-to-1 multiplexer (core)
Four AND gates feeding an OR — the heart of a 4:1 mux.
Chemistry & PhysicsPhysics — Logic: SR latch (NOR)
Cross-coupled NOR gates forming a set-reset latch.
Chemistry & PhysicsPhysics — Logic: 2-to-4 decoder (core)
Two inputs and an inverter pair feeding four AND outputs.
Chemistry & PhysicsPhysics — Logic: 3-input majority voter
Outputs 1 when at least two of three inputs are high.
Chemistry & PhysicsPhysics — Logic: XOR from basic gates
Building XOR from AND, OR and NOT gates.
Chemistry & PhysicsPhysics — Logic: half subtractor
Difference = A XOR B, borrow = (NOT A) AND B.
Chemistry & PhysicsPhysics — Logic: AND-OR-Invert
Two AND gates feeding a NOR (an AOI gate).
Chemistry & PhysicsEngineering — Logic: full subtractor
Difference and borrow for three input bits.
Chemistry & PhysicsEngineering — Logic: 3-bit Parity
An XOR chain computing the parity bit.
Chemistry & PhysicsPhysics — Logic: 4-to-2 priority encoder
Encodes the highest active input line into two bits.
Chemistry & PhysicsPhysics — Logic: 1-bit comparator
Tests two bits for equality and which is greater.
Chemistry & PhysicsPhysics — Logic: BCD invalid-code detector
Flags binary inputs above 9 (illegal BCD codes).
Chemistry & PhysicsPhysics — Logic: XOR from NAND gates
The universal NAND gate builds an exclusive-OR.
Chemistry & PhysicsPhysics — Logic: AND from NAND gates
A NAND followed by a NAND inverter gives AND.
Chemistry & PhysicsPhysics — Logic: OR from NAND gates
Inverting both inputs into a NAND yields OR.
Chemistry & PhysicsPhysics — Logic: 1-to-2 demultiplexer
Routes one data input to one of two outputs by a select bit.
Chemistry & PhysicsPhysics — Logic: D latch
A gated D latch from four NAND gates.
Chemistry & PhysicsPhysics — Logic: JK flip-flop
The gate-level structure of a JK flip-flop.
Chemistry & PhysicsPhysics — Logic: T flip-flop
A toggle flip-flop built from AND and NOR gates.
Chemistry & PhysicsPhysics — Logic: 2-bit equality comparator
Two XNORs and an AND test two 2-bit numbers for equality.
Chemistry & PhysicsPhysics — Logic: 1-bit ALU
AND, OR and XOR functions selected onto one output.
Chemistry & PhysicsPhysics — Logic: Binary to Gray Code
A 2-bit binary-to-Gray converter (one XOR).
Chemistry & PhysicsPhysics — Logic: 1-to-4 demultiplexer
Routes one input to one of four outputs via two select bits.
Chemistry & PhysicsPhysics — Logic: controlled adder/subtractor
A mode bit turns a full adder into a subtractor.
Chemistry & PhysicsPhysics — Logic: 3-bit ripple counter
Toggle stages dividing the clock by powers of two.
Chemistry & PhysicsPhysics — Logic: parity (XOR tree)
A tree of XOR gates computes 3-input parity.
Chemistry & PhysicsPhysics — Logic: 2-to-4 line decoder
Two address lines activate one of four outputs.
Chemistry & PhysicsPhysics — Logic: tristate bus
Enabled buffers drive a shared bus line.
Chemistry & PhysicsPhysics — Logic: master-slave flip-flop
Two latches in series give edge-triggered behaviour.
Chemistry & PhysicsPhysics — Logic: 4-bit shift register
Data ripples through four stages on each clock.
Chemistry & PhysicsPhysics — Logic: mod-3 counter
A counter that resets after three clock pulses.
Chemistry & PhysicsPhysics — Logic: Johnson counter
A twisted-ring counter feeding back the inverted output.
Chemistry & PhysicsPhysics — Logic: ring counter
A single token circulating around the stages.
Chemistry & PhysicsPhysics — Logic: up/down counter control
Direction logic selecting count-up or count-down.
Chemistry & PhysicsPhysics — SR Latch (NOR)
Cross-coupled NOR gates form a set-reset latch.
Scientific PlotsPhysics — 2-to-4 Line Decoder
Two inputs select one of four outputs.
Scientific PlotsPhysics — 1-bit Comparator
Outputs for A greater, equal and less than B.
Scientific PlotsPhysics — 2-to-1 Multiplexer
Select line S routes A or B to the output.
Scientific PlotsPhysics — 4-to-1 Multiplexer
Two select lines route one of four inputs.
Scientific PlotsPhysics — 3-to-8 Line Decoder
Three inputs select one of eight outputs.
Scientific PlotsPhysics — Majority Voter (2 of 3)
Output is high when at least two inputs are high.
Scientific PlotsPhysics — 8-to-3 Encoder
Eight inputs encoded to a 3-bit binary output.
Scientific PlotsPhysics — Tri-state Buffer
A buffer whose output is gated by an enable line.
Scientific PlotsPhysics — 4-to-2 Priority Encoder
Encodes the highest-priority active input.
Scientific PlotsPhysics — 2-bit Binary Adder
A half adder and full adder in cascade.
Scientific PlotsPhysics — Even Parity Generator
The parity bit is the XOR of the data bits.
Scientific PlotsPhysics — 1-to-2 Demultiplexer
Select line routes the input to one of two outputs.
Scientific PlotsPhysics — 1-bit Equality Comparator
An XNOR gate detects when two bits are equal.
Scientific PlotsPhysics — OR from NAND Gates
Invert both inputs, then NAND them.
Scientific PlotsPhysics — NOT from a NOR Gate
Tie both NOR inputs together to invert.
Scientific PlotsPhysics — SR Latch (NAND)
Cross-coupled NAND gates form an active-low latch.
Scientific Plots