5-Stage CPU Pipeline

flowchart LR
IF[Fetch\nIF] --> ID[Decode\nID]
ID --> EX[Execute\nEX]
EX --> MEM[Memory\nMEM]
MEM --> WB[Write-back\nWB]
EX -.->|forward EX/MEM| EX
MEM -.->|forward MEM/WB| EX
HD[Hazard detect] -.-> ID
HD -.->|stall| IF
classDef stage fill:#dbeafe,stroke:#1e3a8a;
classDef ctrl fill:#fef3c7,stroke:#92400e;
class IF,ID,EX,MEM,WB stage
class HD ctrl