Memory Hierarchy
Registers → L1/L2/L3 cache → DRAM → SSD → cloud — latency annotated.
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flowchart LR
R[Registers\n~0.3 ns] --> L1[L1 cache\n~1 ns]
L1 --> L2[L2 cache\n~4 ns]
L2 --> L3[L3 cache\n~12 ns]
L3 --> DRAM[(DRAM\n~100 ns)]
DRAM --> SSD[(NVMe SSD\n~100 µs)]
SSD --> HDD[(HDD\n~10 ms)]
HDD --> Net[(Cloud / network\n~100 ms)]
classDef fast fill:#dcfce7,stroke:#166534;
classDef mid fill:#fef3c7,stroke:#92400e;
classDef slow fill:#fee2e2,stroke:#991b1b;
class R,L1,L2 fast
class L3,DRAM mid
class SSD,HDD,Net slow