Packet & bit fields
Protocol headers and register bit-field layouts at 8, 16, 32 or 64 bits a word, in either bit order and saying which is in force. Checks the layout rather than just drawing it: overlapping fields, unclaimed bit runs and fields that overflow the declared extent are computed and named.
In the same space
Most users come to Packet & bit fields from packetdiag, bytefield-svg, WaveDrom (bitfields) or Protocol Builder. flowss runs this engine in the browser — no install, shareable via URL, exportable to PNG / SVG / PDF / source.
Syntax at a glance
title "IPv4 header"
width 32
bitorder msb
0-3: Version = 4
4-7: IHL
16-31: Total lengthPaste this in the Studio code pane to see Packet & bit fields render live. The full grammar is at the upstream-docs link above.
Sample templates
All 10 →The header every network diagram starts from, drawn at 32 bits a word in RFC bit order with the absolute bit indices on the ruler. Complete: every bit of the five fixed words is claimed, so the engine reports no gaps and the reader can trust that the layout is the whole layout.
Twenty bytes of TCP with each control flag on its own bit, which is the part a prose description always compresses into 'flags' and the part anyone reading a capture actually needs. Written with run-length fields after the first word to show the two notations mixing.
Two MAC addresses and an EtherType, which is the smallest useful demonstration of a field that wraps across word boundaries: a 48-bit address on a 32-bit word does not fit in one row and is drawn split rather than flagged, because wrapping is the layout working and not a defect. It also declares no extent, so the engine says the trailing sixteen bits of the last word are outside the layout rather than unallocated inside it — two states that must not look the same.
The whole of UDP in two words, and the clearest example of the run-length form: four consecutive sixteen-bit fields written as `+16:` rather than as absolute ranges, with the cursor doing the arithmetic so a later insertion does not require renumbering everything after it.
A peripheral control register in LSB-first order, which is how every datasheet in the world numbers bits and the opposite of the RFC convention the protocol templates use. Reserved bits are declared with their required value rather than left out, so the layout has no unclaimed holes and firmware written from it will not leave a reserved bit floating.
A narrower word width, which is the setting people forget exists and then draw a 16-bit register on a 32-bit grid. Sixteen bits a word, LSB order, every bit accounted for — including the two reserved runs, because a reserved bit that is simply absent from the drawing is indistinguishable from one nobody thought about.
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