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Packet & bit fields templates

Packet — 32-bit Control Register (datasheet order)

A peripheral control register in LSB-first order, which is how every datasheet in the world numbers bits and the opposite of the RFC convention the protocol templates use. Reserved bits are declared with their required value rather than left out, so the layout has no unclaimed holes and firmware written from it will not leave a reserved bit floating.

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Template previewPacket & bit fields
UART control register (CR1)32-bit words · 1 word · 32 bits laid out · 24 fields · ruler shows ABSOLUTE bit indicesLSB-first: bit 0 is the least significant bit of each 32-bit word, drawn rightmost; indices decrease to the right.In both orders the most significant bit of a word is the leftmost column — only the numbering flips.Layout checks passed — 24 fields, 1 word, 32 bits: no gaps, no overlaps, nothing past the last word.MSBLSBword 0bits 0–31+0B313029282726252423222120191817161514131211109876543210UEbi…U…bi…REbi…TEbi…I…bi…R…bi…T…bi…T…bi…P…bi…PSbi…P…bi…W…bi…M0bi…M…bi…C…bi…O…bi…DEDTbits 16–20 · 5bR…bi…DEATbits 22–26 · 5bR…bi…M1bi…R…bi…R…bi…R…bi…No overlaps: each of the 32 checked bits belongs to at most one field.No gaps: bits 0–31 fully covered by 24 fields.Every field ends inside the 1-word layout.

Make it your own.

title "UART control register (CR1)"
width 32
bitorder lsb
words 1

0:     UE       = 1
1:     UESM
2:     RE
3:     TE
4:     IDLEIE
5:     RXNEIE
6:     TCIE
7:     TXEIE
8:     PEIE
9:     PS
10:    PCE
11:    WAKE
12:    M0
13:    MME
14:    CMIE
15:    OVER8
16-20: DEDT
21:    Reserved = 0
22-26: DEAT
27:    Reserved = 0
28:    M1
29:    Reserved = 0
30:    Reserved = 0
31:    RXFFIE