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Packet & bit fields templates

Packet — 16-bit Status Register with Read-Only Flags

A narrower word width, which is the setting people forget exists and then draw a 16-bit register on a 32-bit grid. Sixteen bits a word, LSB order, every bit accounted for — including the two reserved runs, because a reserved bit that is simply absent from the drawing is indistinguishable from one nobody thought about.

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ADC status register16-bit words · 1 word · 16 bits laid out · 13 fields · ruler shows ABSOLUTE bit indicesLSB-first: bit 0 is the least significant bit of each 16-bit word, drawn rightmost; indices decrease to the right.In both orders the most significant bit of a word is the leftmost column — only the numbering flips.Layout checks passed — 13 fields, 1 word, 16 bits: no gaps, no overlaps, nothing past the last word.MSBLSBword 0bits 0–15+0B1514131211109876543210ADRDYbit 0…EOSMPbit 1…EOCbit 2…EOSbit 3…OVRbit 4…JEOCbit 5…JEOSbit 6…AWD1bit 7…AWD2bit 8…AWD3bit 9…Rese…bit 1…JQOVFbit 1…Reservedbits 12–15 = 0No overlaps: each of the 16 checked bits belongs to at most one field.No gaps: bits 0–15 fully covered by 13 fields.Every field ends inside the 1-word layout.

Make it your own.

title "ADC status register"
width 16
bitorder lsb
words 1

0:     ADRDY
1:     EOSMP
2:     EOC
3:     EOS
4:     OVR
5:     JEOC
6:     JEOS
7:     AWD1
8:     AWD2
9:     AWD3
10:    Reserved = 0
11:    JQOVF
12-15: Reserved = 0