Synchronous FIFO

library ieee;
use ieee.std_logic_1164.all;

entity sync_fifo is
  generic (
    DEPTH : positive := 16;
    WIDTH : positive := 32
  );
  port (
    --# {{clocks|Clock & Reset}}
    clk    : in  std_logic;
    rst_n  : in  std_logic;
    --# {{write|Write Interface}}
    wr_en  : in  std_logic;
    wr_data: in  std_logic_vector(WIDTH-1 downto 0);
    full   : out std_logic;
    --# {{read|Read Interface}}
    rd_en  : in  std_logic;
    rd_data: out std_logic_vector(WIDTH-1 downto 0);
    empty  : out std_logic;
    --# {{status|Status}}
    count  : out std_logic_vector(7 downto 0)
  );
end entity;