Symbolator — UART Transceiver With Byte Interface (VHDL)

A UART core's symbol: generics for the system clock and baud rate, a valid/ready byte stream on the transmit side, a valid byte plus framing and overrun error flags on the receive side, and the two serial pins. The serial pins sit in their own group so the board-level connection is obvious.

Symbolator (HDL)Architecture Symbolator (HDL) syntax docs

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library ieee;
use ieee.std_logic_1164.all;

entity uart is
  generic (
    CLK_FREQ_HZ : positive := 100000000;
    BAUD_RATE   : positive := 115200
  );
  port (
    --# {{clocks|Clock and reset}}
    clk          : in  std_logic;
    rst          : in  std_logic;
    --# {{data|Transmit byte}}
    tx_data      : in  std_logic_vector(7 downto 0);
    tx_valid     : in  std_logic;
    tx_ready     : out std_logic;
    --# {{data|Receive byte}}
    rx_data      : out std_logic_vector(7 downto 0);
    rx_valid     : out std_logic;
    rx_frame_err : out std_logic;
    rx_overrun   : out std_logic;
    --# {{control|Serial pins}}
    uart_rxd     : in  std_logic;
    uart_txd     : out std_logic
  );
end entity uart;