Symbolator (HDL)

Compatible with Symbolator

Render block symbols from VHDL / Verilog component declarations. Paste an entity or module header and get a neatly drawn symbol with grouped, aligned port pins — the kind of figure that lives in chip datasheets and FPGA documentation.

Templates

Source language

vhdl

Workstation

Studio

Engine id

symbolator

Open in Studio Upstream docs

In the same space

Most users come to Symbolator (HDL) from Quartus symbol view (static) or Vivado symbol export. flowss runs this engine in the browser — no install, shareable via URL, exportable to PNG / SVG / PDF / source.

Syntax at a glance

entity adder is
  port (
    a, b : in std_logic_vector(7 downto 0);
    s    : out std_logic_vector(8 downto 0)
  );
end entity;

Paste this in the Studio code pane to see Symbolator (HDL) render live. The full grammar is at the upstream-docs link above.

Sample templates

All 7 →

architecture

Up/down counter (VHDL)

Parameterised counter entity — symbol with grouped clock/control and data ports.

architecture

Synchronous FIFO

Classic FIFO block symbol — write/read interfaces with status flags.

architecture

Symbolator — AXI4-Lite Register Slave (VHDL)

The block symbol of an AXI4-Lite slave register file with all five AXI channels grouped as an FPGA datasheet draws them — write address, write data, write response, read address and read data — plus clock, active-low reset and an interrupt output. Widths follow the generics, with the write strobe one bit per data byte.

architecture

Symbolator — UART Transceiver With Byte Interface (VHDL)

A UART core's symbol: generics for the system clock and baud rate, a valid/ready byte stream on the transmit side, a valid byte plus framing and overrun error flags on the receive side, and the two serial pins. The serial pins sit in their own group so the board-level connection is obvious.

architecture

Symbolator — SPI Master With Configurable Mode (VHDL)

A parameterised SPI master: word width, clock divider and slave-select count as generics, CPOL and CPHA as run-time inputs so one block serves all four SPI modes, a start/busy/done handshake for the transfer word, and the SCLK, MOSI, MISO and one-hot active-low chip-select pins.

architecture

Symbolator — True Dual-Port Block RAM (VHDL)

A true dual-port RAM as inferred into FPGA block RAM: two fully independent ports, each with its own clock, enable, byte-write enables, address and data in and out, so the symbol reads as two mirror-image interfaces. Depth is 2^ADDR_WIDTH words and the write-enable width is one bit per byte of data.

Engine reference: symbolator · ← Browse all engines · Quick-start guide