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7 templates

Symbolator (HDL) templates

Render block symbols from VHDL / Verilog component declarations. Paste an entity or module header and get a neatly drawn symbol with grouped, aligned port pins — the kind of figure that lives in chip datasheets and FPGA documentation.

Symbolator (HDL) syntax reference

  • Up/down counter (VHDL)

    Parameterised counter entity — symbol with grouped clock/control and data ports.

    Architecture

  • Synchronous FIFO

    Classic FIFO block symbol — write/read interfaces with status flags.

    Architecture

  • Symbolator — AXI4-Lite Register Slave (VHDL)

    The block symbol of an AXI4-Lite slave register file with all five AXI channels grouped as an FPGA datasheet draws them — write address, write data, write response, read address and read data — plus clock, active-low reset and an interrupt output. Widths follow the generics, with the write strobe one bit per data byte.

    Architecture

  • Symbolator — UART Transceiver With Byte Interface (VHDL)

    A UART core's symbol: generics for the system clock and baud rate, a valid/ready byte stream on the transmit side, a valid byte plus framing and overrun error flags on the receive side, and the two serial pins. The serial pins sit in their own group so the board-level connection is obvious.

    Architecture

  • Symbolator — SPI Master With Configurable Mode (VHDL)

    A parameterised SPI master: word width, clock divider and slave-select count as generics, CPOL and CPHA as run-time inputs so one block serves all four SPI modes, a start/busy/done handshake for the transfer word, and the SCLK, MOSI, MISO and one-hot active-low chip-select pins.

    Architecture

  • Symbolator — True Dual-Port Block RAM (VHDL)

    A true dual-port RAM as inferred into FPGA block RAM: two fully independent ports, each with its own clock, enable, byte-write enables, address and data in and out, so the symbol reads as two mirror-image interfaces. Depth is 2^ADDR_WIDTH words and the write-enable width is one bit per byte of data.

    Architecture

  • Symbolator — FIR Filter With AXI4-Stream Interfaces (VHDL)

    A streaming FIR filter's symbol: tap count and sample and coefficient widths as generics, an AXI4-Stream slave input and master output (tdata, tvalid, tready, tlast), and a coefficient-load port. The output is wider than the input by the coefficient width plus growth bits, as a full-precision FIR accumulator requires.

    Architecture