Symbolator — SPI Master With Configurable Mode (VHDL)

A parameterised SPI master: word width, clock divider and slave-select count as generics, CPOL and CPHA as run-time inputs so one block serves all four SPI modes, a start/busy/done handshake for the transfer word, and the SCLK, MOSI, MISO and one-hot active-low chip-select pins.

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library ieee;
use ieee.std_logic_1164.all;

entity spi_master is
  generic (
    DATA_WIDTH : positive := 16;
    CLK_DIV    : positive := 4;
    NUM_SS     : positive := 2
  );
  port (
    --# {{clocks|Clock and reset}}
    clk     : in  std_logic;
    rst_n   : in  std_logic;
    --# {{control|Mode and control}}
    cpol    : in  std_logic;
    cpha    : in  std_logic;
    ss_sel  : in  std_logic_vector(NUM_SS-1 downto 0);
    start   : in  std_logic;
    busy    : out std_logic;
    done    : out std_logic;
    --# {{data|Transfer word}}
    tx_word : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    rx_word : out std_logic_vector(DATA_WIDTH-1 downto 0);
    --# {{data|SPI bus}}
    sclk    : out std_logic;
    mosi    : out std_logic;
    miso    : in  std_logic;
    ss_n    : out std_logic_vector(NUM_SS-1 downto 0)
  );
end entity spi_master;