Symbolator — AXI4-Lite Register Slave (VHDL)

The block symbol of an AXI4-Lite slave register file with all five AXI channels grouped as an FPGA datasheet draws them — write address, write data, write response, read address and read data — plus clock, active-low reset and an interrupt output. Widths follow the generics, with the write strobe one bit per data byte.

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library ieee;
use ieee.std_logic_1164.all;

entity axil_regs is
  generic (
    C_S_AXI_DATA_WIDTH : integer := 32;
    C_S_AXI_ADDR_WIDTH : integer := 6
  );
  port (
    --# {{clocks|Clock and reset}}
    s_axi_aclk    : in  std_logic;
    s_axi_aresetn : in  std_logic;
    --# {{data|Write address}}
    s_axi_awaddr  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
    s_axi_awprot  : in  std_logic_vector(2 downto 0);
    s_axi_awvalid : in  std_logic;
    s_axi_awready : out std_logic;
    --# {{data|Write data}}
    s_axi_wdata   : in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
    s_axi_wstrb   : in  std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
    s_axi_wvalid  : in  std_logic;
    s_axi_wready  : out std_logic;
    --# {{data|Write response}}
    s_axi_bresp   : out std_logic_vector(1 downto 0);
    s_axi_bvalid  : out std_logic;
    s_axi_bready  : in  std_logic;
    --# {{data|Read address}}
    s_axi_araddr  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
    s_axi_arprot  : in  std_logic_vector(2 downto 0);
    s_axi_arvalid : in  std_logic;
    s_axi_arready : out std_logic;
    --# {{data|Read data}}
    s_axi_rdata   : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
    s_axi_rresp   : out std_logic_vector(1 downto 0);
    s_axi_rvalid  : out std_logic;
    s_axi_rready  : in  std_logic;
    --# {{control|Interrupt}}
    irq           : out std_logic
  );
end entity axil_regs;