Symbolator — FIR Filter With AXI4-Stream Interfaces (VHDL)

A streaming FIR filter's symbol: tap count and sample and coefficient widths as generics, an AXI4-Stream slave input and master output (tdata, tvalid, tready, tlast), and a coefficient-load port. The output is wider than the input by the coefficient width plus growth bits, as a full-precision FIR accumulator requires.

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library ieee;
use ieee.std_logic_1164.all;

entity fir_axis is
  generic (
    NUM_TAPS    : positive := 64;
    DATA_WIDTH  : positive := 16;
    COEF_WIDTH  : positive := 18;
    GROWTH_BITS : natural  := 6
  );
  port (
    --# {{clocks|Clock and reset}}
    aclk          : in  std_logic;
    aresetn       : in  std_logic;
    --# {{data|Sample input (AXI4-Stream slave)}}
    s_axis_tdata  : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    s_axis_tvalid : in  std_logic;
    s_axis_tready : out std_logic;
    s_axis_tlast  : in  std_logic;
    --# {{data|Filtered output (AXI4-Stream master)}}
    m_axis_tdata  : out std_logic_vector(DATA_WIDTH+COEF_WIDTH+GROWTH_BITS-1 downto 0);
    m_axis_tvalid : out std_logic;
    m_axis_tready : in  std_logic;
    m_axis_tlast  : out std_logic;
    --# {{control|Coefficient load}}
    coef_wr       : in  std_logic;
    coef_addr     : in  std_logic_vector(5 downto 0);
    coef_data     : in  std_logic_vector(COEF_WIDTH-1 downto 0)
  );
end entity fir_axis;