Up/down counter (VHDL)

Parameterised counter entity — symbol with grouped clock/control and data ports.

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Make it your own.

library ieee;
use ieee.std_logic_1164.all;

entity counter is
  generic (
    WIDTH : positive := 8
  );
  port (
    --# {{clocks|Clocking}}
    clk      : in  std_logic;
    rst_n    : in  std_logic;
    --# {{control|Control}}
    enable   : in  std_logic;
    up_down  : in  std_logic;
    load     : in  std_logic;
    --# {{data|Data}}
    data_in  : in  std_logic_vector(WIDTH-1 downto 0);
    count    : out std_logic_vector(WIDTH-1 downto 0);
    --# {{flags|Flags}}
    overflow : out std_logic;
    zero     : out std_logic
  );
end entity;