Symbolator — True Dual-Port Block RAM (VHDL)

A true dual-port RAM as inferred into FPGA block RAM: two fully independent ports, each with its own clock, enable, byte-write enables, address and data in and out, so the symbol reads as two mirror-image interfaces. Depth is 2^ADDR_WIDTH words and the write-enable width is one bit per byte of data.

Symbolator (HDL)Architecture Symbolator (HDL) syntax docs

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Make it your own.

library ieee;
use ieee.std_logic_1164.all;

entity tdp_ram is
  generic (
    ADDR_WIDTH : positive := 10;
    DATA_WIDTH : positive := 32
  );
  port (
    --# {{data|Port A}}
    clka  : in  std_logic;
    ena   : in  std_logic;
    wea   : in  std_logic_vector((DATA_WIDTH/8)-1 downto 0);
    addra : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    dina  : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    douta : out std_logic_vector(DATA_WIDTH-1 downto 0);
    --# {{data|Port B}}
    clkb  : in  std_logic;
    enb   : in  std_logic;
    web   : in  std_logic_vector((DATA_WIDTH/8)-1 downto 0);
    addrb : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    dinb  : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    doutb : out std_logic_vector(DATA_WIDTH-1 downto 0)
  );
end entity tdp_ram;